A clock generation method which uses a conventional PLL (Phase-locked loop) is disclosed in, for example, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 27, NO 11, November 1992 (hereinbelow, referred to as the “prior art example A”).
FIG. 2 illustrates the construction of a clock generation unit which employs the conventional PLL. A reference clock signal fext input to the PLL from outside the circuit. The PLL includes the following: “PFD”, a phase/frequency comparator; “CP”, a charge pump; “LPF”, a low-pass filter; “VOC0”, a voltage-controlled oscillator; “DIVN”, a 1/N frequency divider; “DIV2”, a ½ frequency divider; and “NO”, a clock distribution network. The details of each of these circuit elements is omitted.
The difference between the phases or frequencies of the reference clock signal fext and an internal clock signal fint is compared by the phase/frequency comparator PFD, from which an error signal UP or DN is output. The error signal is converted into an analog signal by the charge pump CP, and the high frequency components of the signal are removed by the low-pass filter LPF. The resulting signal is input to the voltage-controlled oscillator VCO0 as an oscillation-frequency control signal VC. The oscillation output of the voltage-controlled oscillator VCO0 is divided by the frequency divider DIV2 into an oscillation output fint0 whose frequency is half the frequency of the former oscillation output and whose duty ratio is 50%, and which is input to the clock distribution network N0.
The return signal fint from the clock distribution system has its frequency divided by the 1/N frequency divider DIVN. The resulting signal is input to the phase/frequency comparator PFD. The phases of the reference clock fext and internal clock fint are locked by such a phase-locked loop PLL0, and the frequency of the signal fint becomes N times that of the signal fext.